Junior Verification Engineer

תיאור התפקיד

Junior Verification Engineer

דרישות התפקיד

B.Sc in Electrical Engineering graduating with honors.

Good knowledge of chip architecture/design.

Knowledge in Verification flow, System Verilog, UVM – an advantage.

  Good programming skills in Verilog, VHDL, C, Assembly, Perl.

Personal Attributes:

Creative, dynamic thinker, open minded with strong problem solving skills.

Fast learner of new technologies and standards.

Good communication and teamwork skills.

Good written and spoken English communication.

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